Riya Joshi Email
ASIC Design Engineer @ NVIDIA
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Riya Joshi Location
- United States
Riya Joshi Work
- ASIC Design Engineer @ (January 2025 - Present)
- Masters Student @ (September 2023 - June 2025)
- ASIC Design Intern @ (June 2024 - September 2024)
- Firmware Verification Engineer @ (April 2022 - July 2023)
- Editorial Team Lead @ Electrobytes - The Official Newsletter of ECE Department, JSSATEN (May 2017 - May 2019)
Riya Joshi Education
- UC San Diego Jacobs School of Engineering
Master of Science - MS (Electrical and Computer Engineering)
2023-2025 - JSS ACADEMY OF TECHNICAL EDUCATION, NOIDA
B-Tech (Electronics and Communications Engineering)
2015-2019 - ASSISI Convent Senior Secondary School, Noida
Senior Secondary
2009-2015
Riya Joshi Skills
- ASIC/FPGA
- Application-Specific Integrated Circuits (ASIC)
- Cadence Virtuoso
- Communication
- Core Java
- Digital Designs
- Digital IC Design
- Editing
- Electrical Engineering
- Electronics
- Field-Programmable Gate Arrays (FPGA)
- Linux
- Python (Programming Language)
- RTL Design
- RTL Verification
- SystemVerilog
- Team Leadership
- Team Management
- UVM
- Universal Verification Methodology (UVM)
- VLSI basics
- Verilog
- Very-Large-Scale Integration (VLSI)
Riya Joshi Summary
- Riya Joshi, based in United States, is currently a ASIC Design Engineer at NVIDIA. Riya Joshi brings experience from previous roles at UC San Diego, NVIDIA, RAILBIT and Electrobytes - The Official Newsletter of ECE Department, JSSATEN. Riya Joshi holds a 2023 - 2025 Master of Science - MS in Electrical and Computer Engineering @ UC San Diego Jacobs School of Engineering. With a robust skill set that includes ASIC/FPGA, Application-Specific Integrated Circuits (ASIC), Cadence Virtuoso, Communication, Core Java and more. Riya Joshi has 2 emails on RocketReach.
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