Ritesh K Location
- Hsinchu, TW
Ritesh K Work
- 2015 - now Principal Engineer @
- 2012 - 2015 Senior Technical Consultant for Low Power Physical Implementation @
- 2010 - 2012 Senior Staff Engineer @
- 2007 - 2010 Design Engineer @
- 2004 - 2007 Design Engineer @
Ritesh K Education
- Birla Institute of Technology and Science, Pilani
Master's degree (Microelectonics)
2007 - 2009 - Babasaheb Bhimrao Ambedkar University
Bachelor of Technology (B.Tech.) (Electronics and Communications Engineering)
1998 - 2002
Ritesh K Skills
- Physical Design
- SoC
- Static Timing Analysis
- ASIC
- Verilog
- VLSI
- EDA
- RTL design
- Semiconductors
- Timing Closure
- VHDL
- Functional Verification
- SystemVerilog
- TCL
- Debugging
- Perl
- CMOS
- IC
- Integrated Circuit Design
- Simulations
- FPGA
- Cadence Virtuoso
- Circuit Design
- Analog
- Mixed Signal
- Low-power Design
- Digital Signal Processors
- Analog Circuit Design
- Microprocessors
- Logic Design
- System on a Chip Soc
- Very Large Scale Integration Vlsi
- Management
- Low Power Design
- Engineering
- Illustrator
- Business Analysis
- Customer Service
- Integrated Circuits Ic
- Manufacturing
- Application Specific Integrated Circuits Asic
- Strategy
Ritesh K Summary
- Ritesh K, based in Hsinchu, TW, is currently a Principal Engineer at TSMC. Ritesh K brings experience from previous roles at Synapse Design Inc., IBM, AMD and Texas Instruments. Ritesh K holds a 2007 - 2009 Master's degree in Microelectonics @ Birla Institute of Technology and Science, Pilani. With a robust skill set that includes Physical Design, SoC, Static Timing Analysis, ASIC, Verilog and more. Ritesh K has 2 emails on RocketReach.
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