Ritesh Garg Email & Phone Number
Senior Technical Manager
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Ritesh Garg Location
- Mountain View, CA, US
Ritesh Garg Work
- Senior Technical Manager @ MediaTek (April 2026 - Present)
- Circuit Design Engineer @ (July 2024 - April 2026)
- Senior Technical Manager @ MediaTek (June 2020 - July 2024)
- Technical Manager @ MediaTek (July 2019 - May 2020)
- Manager @ (June 2018 - June 2019)
- Staff R and D Enginner @ (May 2015 - June 2018)
- Sr. R and D Engineer @ (October 2012 - May 2015)
- Sr. R and D Engineer @ (April 2012 - September 2012)
- senior design engineer @ Texas Instruments (May 2008 - April 2012)
- design engineer @ (March 2006 - April 2008)
- design engineer @ (January 2005 - January 2006)
Ritesh Garg Education
- Indian Institute of Technology, Bombay
MTech (Microelectronics)
2003-2005 - Visvesvaraya National Institute of Technology
BTech (Electronics)
1999-2003 - Bal bharti
Ritesh Garg Skills
- Memory Design
- Circuit Design
- Compiler Design
- SRAM
- CMOS
- Memory Test
- Compiler Construction
- SoC
- VLSI
- System on a Chip (SoC)
- Static Timing Analysis
- bitcell
- register files
- System On A Chip Soc
- System on a Chip
Ritesh Garg Summary
- Ritesh Garg, based in Mountain View, CA, US, is currently a Senior Technical Manager at MediaTek. Ritesh Garg brings experience from previous roles at Apple, MediaTek and Synopsys Inc. Ritesh Garg holds a 2003 - 2005 MTech in Microelectronics @ Indian Institute of Technology, Bombay. With a robust skill set that includes Memory Design, Circuit Design, Compiler Design, SRAM, CMOS and more. Ritesh Garg has 1 emails and 2 mobile phone numbers on RocketReach.
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