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Ritesh Garg Location
Mountain View, CA, US
Ritesh Garg Work
2026 -now Senior Technical Manager @
2024 -2026 Circuit Design Engineer @
2020 -2024 Senior Technical Manager @
2019 -2020 Technical Manager @
2018 -2019 Manager @
2015 -2018 Staff R and D Enginner @
2012 -2015 Sr. R and D Engineer @
2012 -2012 Sr. R and D Engineer @
2008 -2012 senior design engineer @
2006 -2008 design engineer @
2005 -2006 design engineer @
Ritesh Garg Education
Indian Institute of Technology, Bombay
MTech (Microelectronics)
2003-2005
Visvesvaraya National Institute of Technology
BTech (Electronics)
1999-2003
Bal bharti
Ritesh Garg Skills
Memory Design
Circuit Design
Compiler Design
SRAM
CMOS
Memory Test
Compiler Construction
SoC
VLSI
System on a Chip (SoC)
Static Timing Analysis
bitcell
register files
System On A Chip Soc
System on a Chip
Ritesh Garg Summary
Ritesh Garg, based in Mountain View, CA, US, is currently a Senior Technical Manager at MediaTek. Ritesh Garg brings experience from previous roles at Apple, MediaTek and Synopsys Inc. Ritesh Garg holds a 2003 - 2005 MTech in Microelectronics @ Indian Institute of Technology, Bombay. With a robust skill set that includes Memory Design, Circuit Design, Compiler Design, SRAM, CMOS and more. Ritesh Garg has 1 emails and 2 mobile phone numbers on RocketReach.
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