Ritesh Garg Email & Phone Number

Circuit Design Engineer @ Apple

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Ritesh Garg Location

Mountain View, CA, US

Ritesh Garg Work

2024 - now Circuit Design Engineer @
2020 - 2024 Senior Technical Manager @
2019 - 2020 Technical Manager @
2018 - 2019 Manager @
2015 - 2018 Staff R and D Enginner @
2012 - 2015 Sr. R and D Engineer @
2012 - 2012 Sr. R and D Engineer @
2008 - 2012 senior design engineer @
2006 - 2008 design engineer @
2005 - 2006 design engineer @

Ritesh Garg Education

Indian Institute of Technology, Bombay 2003 - 2005
Visvesvaraya National Institute of Technology 1999 - 2003
Bal bharti

Ritesh Garg Skills

Memory Design
Circuit Design
Compiler Design
SRAM
CMOS
Memory Test
Compiler Construction
SoC
VLSI
System on a Chip (SoC)
Static Timing Analysis
bitcell
register files
System On A Chip Soc
System on a Chip

Ritesh Garg Summary

Ritesh Garg, based in Mountain View, CA, US, is currently a Circuit Design Engineer at Apple. Ritesh Garg brings experience from previous roles at MediaTek and Synopsys Inc. Ritesh Garg holds a 2003 - 2005 Indian Institute of Technology, Bombay. With a robust skill set that includes Memory Design, Circuit Design, Compiler Design, SRAM, CMOS and more. Ritesh Garg has 1 emails and 2 mobile phone numbers on RocketReach.

Ritesh Garg Emails

Found 1 email

Ritesh Garg Phone Numbers

Found 3 phone numbers

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Others Named Ritesh Garg

Ritesh Garg

Circuit Design Engineer

Mountain View, CA, US

gmail.com

+1 408-507-XXXX
+1 408-649-XXXX
+1 650-584-XXXX

Ritesh Garg

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Sunnyvale, CA, US

gmail.com
salesforce.com
salesforce.org

+1 959-938-XXXX
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Ritesh Garg

Vice President

Glasgow, GB

jpmchase.com
jpmorgan.com

+91 76177 5XXXX

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