Ravi Teja Email
Senior Design Verification Engineer @ Elevate Semiconductor
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Ravi Teja Location
- San Diego, CA, US
Ravi Teja Work
- Senior Design Verification Engineer @ (May 2026 - Present)
- Senior AMS Verification Engineer @ (March 2022 - January 2026)
- AMS Verification Engineer @ (January 2021 - March 2022)
- VLSI Engineer @ (November 2020 - March 2022)
- Analog Design Engineer @ (September 2018 - November 2020)
- AMS Verification Engineer @ (September 2018 - November 2020)
- Design Trainee @ (May 2018 - August 2018)
- Technical Assistant @ (August 2014 - April 2015)
Ravi Teja Education
- Birla Institute of Technology and Science, Pilani
Master of Technology - MTech (Microelectronics)
2019-2021 - Karunya Institute of Technology and Sciences
Bachelor of Technology - BTech (Electrical, Electronics and Communications Engineering)
2014-2018
Ravi Teja Skills
- Analog Circuit Design
- Application-Specific Integrated Circuits (ASIC)
- Basic knowledge on perl
- C
- Cadence Virtuoso Layout Editor
- Circuit Design
- Debugging
- Digital Electronics
- Electronics
- Field-Programmable Gate Arrays (FPGA)
- Linux
- Management
- Microsoft Excel
- Microsoft Office
- Microsoft PowerPoint
- Microsoft Word
- Perl
- Programming
- Python (Programming Language)
- RTL Coding
- VHDL
- Verilog
- Very-Large-Scale Integration (VLSI)
Ravi Teja Summary
- Ravi Teja, based in San Diego, CA, US, is currently a Senior Design Verification Engineer at Elevate Semiconductor. Ravi Teja brings experience from previous roles at Analog Devices, Intel Corporation, Wipro Limited and Tessolve. Ravi Teja holds a 2019 - 2021 Master of Technology - MTech in Microelectronics @ Birla Institute of Technology and Science, Pilani. With a robust skill set that includes Analog Circuit Design, Application-Specific Integrated Circuits (ASIC), Basic knowledge on perl , C, Cadence Virtuoso Layout Editor and more.
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Neha Udaiwal
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Jesse Elder
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