Senior Engineer, UltraSparc microprocessor physical design @ Sun Microsystems
Ramesh Rajagopalan's Education
University of Cincinnati
MS (Computer Engineering)
1992 - 1994
Santa Clara University - Leavey School of Business
MBA (Bringing Technology to Market)
2004 - 2005
Osmania University
Master of Engineering (Electronics and Telecommunication Engg)
University of Madras
Bachelor of Engineering (Electronics and Communication Engg)
Ramesh Rajagopalan's Skills
ASIC
Physical Design
SoC
Microprocessors
Logic Synthesis
TCL
Perl
VLSI
Static Timing Analysis
EDA
Ramesh Rajagopalan's Summary
Ramesh Rajagopalan, based in San Jose, CA, US, is currently a Chip lead for Physical Design at Cisco, bringing experience from previous roles at Texas Instruments and Sun Microsystems. Ramesh Rajagopalan holds a 1992 - 1994 MS in Computer Engineering @ University of Cincinnati. With a robust skill set that includes ASIC, Physical Design, SoC, Microprocessors, Logic Synthesis and more, Ramesh Rajagopalan contributes valuable insights to the industry. Ramesh Rajagopalan has 3 emails on RocketReach.