Prashanth Narayanasetti Email & Phone Number
Physical Design (PD) Lead @ NUVACORE
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Prashanth Narayanasetti Location
- Austin, TX, US
Prashanth Narayanasetti Work
- 2026 -now Physical Design (PD) Lead @
- 2022 -2026 Senior Director, Silicon and Hardware Engineering @
- 2013 -2022 CPU Design Manager @
- 2006 -2013 CPU and SOC Design Engineer @
- 2005 -2006 Design Engineer @
Prashanth Narayanasetti Education
- R. V. College of Engineering, Bangalore
Bachelor of Engineering (B.E.) ( Telecommunications Engineering )
2001-2005
Prashanth Narayanasetti Skills
- Timing Closure
- SoC
- Static Timing Analysis
- VLSI
- ASIC
- Physical Design
- RTL design
- Verilog
- Primetime
- Functional Verification
- EDA
- Low-power Design
- TCL
- Semiconductors
- Logic Synthesis
- Formal Verification
- DRC
- Floorplanning
- Physical Verification
- Clock Tree Synthesis
- Power Management
- LVS
- Processors
- Microprocessors
- Power Analysis
- Cadence
- Timing
- NCSim
- VHDL
- CMOS
- ARM
- SystemVerilog
- Place & Route
- Analog
- IC
- DFT
- Microcontrollers
- Mixed Signal
- RTL coding
- OMAP
- Logic Design
- Integrated Circuit Design
- ModelSim
- Cadence Virtuoso
- ATPG
- Place And Route
- Integrated Circuit
- Design
- Low Power Design
Prashanth Narayanasetti Summary
- Prashanth Narayanasetti, based in Austin, TX, US, is currently a Physical Design (PD) Lead at NUVACORE. Prashanth Narayanasetti brings experience from previous roles at Microsoft, Apple, Texas Instruments and Infineon Technologies. Prashanth Narayanasetti holds a 2001 - 2005 Bachelor of Engineering (B.E.) in Telecommunications Engineering @ R. V. College of Engineering, Bangalore . With a robust skill set that includes Timing Closure, SoC, Static Timing Analysis, VLSI, ASIC and more. Prashanth Narayanasetti has 1 emails and 2 mobile phone numbers on RocketReach.
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