Peter Wu Email & Phone Number
Senior Director, DSP and architecture @ Marvell India
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Peter Wu Location
- Palo Alto, CA, US
Peter Wu Work
- Senior Director, DSP and architecture @ (April 2021 - Present)
- Director Of Engineering, DSP and Architecture @ (April 2016 - April 2021)
- Technical manager, DSP algorithm and architecture @ (April 2010 - April 2016)
- Senior Staff DSP engineer @ (July 2007 - April 2010)
- DMTS @ Agere system (August 2002 - July 2007)
- Design Engineer @ Lucent (April 1999 - May 2002)
- Design Engineer @ Enable Semiconductor (August 1998 - February 1999)
- Design Engineer @ (August 1995 - August 1998)
Peter Wu Education
- 中国科学技术大学
- Georgia Institute of Technology
Peter Wu Skills
- SoC
- IC
- C++
- Mixed Signal
- Verilog
- RTL design
- ASIC
- Semiconductors
- Perl
- Photoshop
- Telecommunications
- Strategic Planning
Peter Wu Summary
- Peter Wu, based in Palo Alto, CA, US, is currently a Senior Director, DSP and architecture at Marvell Semiconductor. Peter Wu brings experience from previous roles at Marvell Semiconductor and Agere system. Peter Wu holds a 中国科学技术大学. With a robust skill set that includes SoC, IC, C++, Mixed Signal, Verilog and more. Peter Wu has 2 emails and 2 mobile phone numbers on RocketReach.
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