Pavan Patel Email & Phone Number
Senior staff Physical Design Engineer @ INNOSILICON
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Pavan Patel Location
- Reading, GB
Pavan Patel Work
- Senior staff Physical Design Engineer @ (March 2025 - Present)
- Staff Engineer @ (June 2022 - March 2025)
- Senior Engineering Consultant @ (August 2020 - June 2022)
- Engineering Consultant @ (July 2019 - August 2020)
- Engineer @ (August 2017 - July 2019)
- Contractor @ (November 2016 - August 2017)
- Engineer @ (January 2015 - November 2016)
- Intern @ (August 2013 - July 2014)
Pavan Patel Education
- GANPAT UNIVERSITY
M.TECH (VLSI DESIGN)
2012-2014 - Rajasthan technical university KOTA
Bachelor of Technology (B.Tech.) (Electronics and Communications Engineering)
2009-2012 - B&B institute of technology, vidhyanagar
Diploma (Electronics and Communications Engineering)
2006-2009
Pavan Patel Skills
- Verilog
- Physical Design
- VLSI
- Static Timing Analysis
- TCL
- C
- CMOS
- Xilinx
- Floorplanning
- Logic Synthesis
- P&R
- DRC
- LVS
- Perl Script
- Shell Scripting
- Linux
- Tcl-Tk
- ERC
- Embedded Systems
- C++
- Microsoft Office
- ASIC
- Application-Specific Integrated Circuits (ASIC)
- Perl
- Very-Large-Scale Integration (VLSI)
- ISO 26262
- Tcl Tk
- Administration
- Very Large Scale Integration
- Application Specific Integrated Circuits
Pavan Patel Summary
- Pavan Patel, based in Reading, GB, is currently a Senior staff Physical Design Engineer at INNOSILICON. Pavan Patel brings experience from previous roles at Sondrel, Sondrel Ltd and MediaTek. Pavan Patel holds a 2012 - 2014 M.TECH in VLSI DESIGN @ GANPAT UNIVERSITY. With a robust skill set that includes Verilog, Physical Design, VLSI, Static Timing Analysis, TCL and more. Pavan Patel has 1 emails on RocketReach.
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