Pavan Patel Email & Phone Number
Senior staff Physical Design Engineer @ INNOSILICON
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Pavan Patel Location
- United Kingdom
Pavan Patel Work
- 2025 - now Senior staff Physical Design Engineer @
- 2022 - 2025 Staff Engineer @
- 2020 - 2022 Senior Engineering Consultant @
- 2019 - 2020 Engineering Consultant @
- 2017 - 2019 Engineer @
- 2016 - 2017 Contractor @
- 2015 - 2016 Engineer @
- 2013 - 2014 Intern @
Pavan Patel Education
- GANPAT UNIVERSITY
M.TECH (VLSI DESIGN)
2012 - 2014 - Rajasthan technical university KOTA
Bachelor of Technology (B.Tech.) (Electronics and Communications Engineering)
2009 - 2012 - B&B institute of technology, vidhyanagar
Diploma (Electronics and Communications Engineering)
2006 - 2009
Pavan Patel Skills
- Verilog
- Physical Design
- VLSI
- Static Timing Analysis
- TCL
- C
- CMOS
- Xilinx
- Floorplanning
- Logic Synthesis
- P&R
- DRC
- LVS
- Perl Script
- Shell Scripting
- Linux
- Tcl-Tk
- ERC
- Embedded Systems
- C++
- Microsoft Office
- ASIC
- Application-Specific Integrated Circuits (ASIC)
- Perl
- Very-Large-Scale Integration (VLSI)
- ISO 26262
- Tcl Tk
- Administration
- Very Large Scale Integration
- Application Specific Integrated Circuits
Pavan Patel Summary
- Pavan Patel, based in United Kingdom, is currently a Senior staff Physical Design Engineer at INNOSILICON. Pavan Patel brings experience from previous roles at Sondrel and MediaTek. Pavan Patel holds a 2012 - 2014 M.TECH in VLSI DESIGN @ GANPAT UNIVERSITY. With a robust skill set that includes Verilog, Physical Design, VLSI, Static Timing Analysis, TCL and more. Pavan Patel has 2 emails on RocketReach.
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