Pavan Meda Email
Programmable IP Verification Engineer @ Altera
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Pavan Meda Location
- Bengaluru, KA, IN
Pavan Meda Work
- Programmable IP Verification Engineer @ (January 2025 - Present)
- Programmable IP Verification Engineer @ (July 2021 - December 2024)
- Senior Staff Engineer @ (November 2018 - July 2021)
- Staff Product Verification Engineer @ (March 2018 - October 2018)
- Senior Verification Engineer @ (December 2016 - February 2018)
- FPGA Engineer @ (October 2012 - December 2016)
- ASIC Verification Engineer @ (July 2011 - September 2012)
Pavan Meda Education
- Jawaharlal Nehru Technological University
M.Tech (VLSI System Design)
2009-2011
Pavan Meda Skills
- SystemVerilog
- Functional Verification
- ASIC
- Verilog
- NCSim
- UVM
- ModelSim
- Open Verification Methodology
- Integrated Circuit Design
- Debugging
- VLSI
- SoC
- VHDL
- Formal Verification
- FPGA
- Logic Design
- VCS
- Field-Programmable Gate Arrays (FPGA)
- Very-Large-Scale Integration (VLSI)
- System on a Chip (SoC)
- Application-Specific Integrated Circuits (ASIC)
- Universal Verification Methodology (UVM)
Pavan Meda Summary
- Pavan Meda, based in Bengaluru, KA, IN, is currently a Programmable IP Verification Engineer at Altera. Pavan Meda brings experience from previous roles at Intel Corporation, SAMSUNG R&D INSTITUTE INDIA - BANGALORE PRIVATE LIMITED and PMC-Sierra is now Microsemi. Pavan Meda holds a 2009 - 2011 M.Tech in VLSI System Design @ Jawaharlal Nehru Technological University. With a robust skill set that includes SystemVerilog, Functional Verification, ASIC, Verilog, NCSim and more. Pavan Meda has 1 emails on RocketReach.
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