Pavan Meda Email
Programmable IP Verification Engineer @ Altera
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Pavan Meda Location
- Bengaluru, KA, IN
Pavan Meda Work
- 2025 -now Programmable IP Verification Engineer @
- 2021 -2024 Programmable IP Verification Engineer @
- 2018 -2021 Senior Staff Engineer @
- 2018 -2018 Staff Product Verification Engineer @
- 2016 -2018 Senior Verification Engineer @
- 2012 -2016 FPGA Engineer @
- 2011 -2012 ASIC Verification Engineer @
Pavan Meda Education
- Jawaharlal Nehru Technological University 2009-2011
Pavan Meda Skills
- SystemVerilog
- Functional Verification
- ASIC
- Verilog
- NCSim
- UVM
- ModelSim
- Open Verification Methodology
- Integrated Circuit Design
- Debugging
- VLSI
- SoC
- VHDL
- Formal Verification
- FPGA
- Logic Design
- VCS
- Field-Programmable Gate Arrays (FPGA)
- Very-Large-Scale Integration (VLSI)
- System on a Chip (SoC)
- Application-Specific Integrated Circuits (ASIC)
- Universal Verification Methodology (UVM)
Pavan Meda Summary
- Pavan Meda, based in Bengaluru, KA, IN, is currently a Programmable IP Verification Engineer at Altera. Pavan Meda brings experience from previous roles at Intel Corporation, SAMSUNG R&D INSTITUTE INDIA - BANGALORE PRIVATE LIMITED and PMC-Sierra is now Microsemi. Pavan Meda holds a 2009 - 2011 Jawaharlal Nehru Technological University. With a robust skill set that includes SystemVerilog, Functional Verification, ASIC, Verilog, NCSim and more. Pavan Meda has 1 emails on RocketReach.
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