Product Engineer @ RCA Solid State (January 1983 - January 1985)
Paul Graves Education
University of Wisconsin-Madison
BSEE (Semiconductors)
1978-1983
Paul Graves Skills
Semiconductor Device
Test Engineering
Yield Management
Cadence Virtuoso
Layout Design
Digital Electronics
Floorplanning
RF
Cadence Virtuoso Xl
Cost Reduction/Avoidance
Analog Circuit Design
BiCMOS
Physical Verification
Design Engineering
Correlation Analysis
Analog
Spectre
Electronics
Parasitic Extraction
Verilog
Integrated Circuit Design
USB
Product Engineering
Electronic Circuit Design
Cadence
Antennas
Circuit Design
Mixed Signal
CMOS
Semiconductor Industry
LVS
Rcx
Design for Manufacturing
Design of Experiments
Monte Carlo Simulation
Circuit Simulation
EDA
Microelectronics
Simulation
Analog Design
Semiconductors
Physical Design
Simulations
Cadence Spectre
Cadence Virtuoso Layout Editor
SPC
Virtuoso
Schematic Capture
Silicon
IC
Paul Graves Summary
Paul Graves, based in McKinney, TX, US, is currently a Layout Design Engineer at IC Enable. Paul Graves brings experience from previous roles at Pregnancy Resources Inc. and Intersil. Paul Graves holds a 1978 - 1983 BSEE in Semiconductors @ University of Wisconsin-Madison. With a robust skill set that includes Semiconductor Device, Test Engineering, Yield Management, Cadence Virtuoso, Layout Design and more. Paul Graves has 1 emails and 2 mobile phone numbers on RocketReach.
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