Pankaj Patel Email & Phone Number
Director, Design Verification @ Astera Labs
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Pankaj Patel Location
- Santa Clara, CA, US
Pankaj Patel Work
- 2024 -now Director, Design Verification @
- 2023 -2025 Principal Design Verification Engineer @
- 2019 -2023 Senior Design Verification Engineer @
- 2013 -2019 Sr. Staff ASIC Verification Engineer @
- 2013 -2013 Hardware Engineer @
- 2011 -2013 Component Design Engineer @
- 2007 -2011 ASIC Verification Engineer @
Pankaj Patel Skills
- SystemVerilog
- Simulations
- Semiconductors
- UVM
- ASIC
- AXI
- SoC
- Verilog
- Open Verification Methodology
- VLSI
- NCSim
- EDA
- ModelSim
- I2C
- Specman
- Debugging
- Verification
- C++
- SAN
- Functional Verification
Pankaj Patel Summary
- Pankaj Patel, based in Santa Clara, CA, US, is currently a Director, Design Verification at Astera Labs. Pankaj Patel brings experience from previous roles at Microsoft, SanDisk, a Western Digital Brand and Cisco Systems. With a robust skill set that includes SystemVerilog, Simulations, Semiconductors, UVM, ASIC and more. Pankaj Patel has 2 emails and 2 mobile phone numbers on RocketReach.
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