Pankaj Patel Email & Phone Number
Director, Design Verification @ Astera Labs
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Pankaj Patel Location
- Santa Clara, CA, US
Pankaj Patel Work
- Director, Design Verification @ (September 2024 - Present)
- Principal Design Verification Engineer @ (June 2023 - May 2025)
- Senior Design Verification Engineer @ (June 2019 - June 2023)
- Sr. Staff ASIC Verification Engineer @ (September 2013 - June 2019)
- Hardware Engineer @ (March 2013 - August 2013)
- Component Design Engineer @ (March 2011 - March 2013)
- ASIC Verification Engineer @ (January 2007 - December 2011)
Pankaj Patel Skills
- ARM
- ASIC
- AXI
- C++
- Debugging
- EDA
- Ethernet
- Functional Verification
- I2C
- Interconnect
- Leadership
- ModelSim
- NCSim
- NVM Express (NVMe)
- Open Verification Methodology
- Simulations
- SoC
- Specman
- System on a Chip (SoC)
- SystemVerilog
- UVM
- VLSI
- Verilog
- dv lead
- Semiconductors
- Verification
- SAN
Pankaj Patel Summary
- Pankaj Patel, based in Santa Clara, CA, US, is currently a Director, Design Verification at Astera Labs. Pankaj Patel brings experience from previous roles at Microsoft, SanDisk, a Western Digital Brand and Cisco Systems. With a robust skill set that includes ARM, ASIC, AXI, C++, Debugging and more. Pankaj Patel has 2 emails and 2 mobile phone numbers on RocketReach.
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