ASIC Physical Design Lead @ (August 2010 - March 2014)
ASIC layout engineer Trainee @ (September 2008 - September 2009)
Niraj Jani Education
Sardar Patel University
Master of Science - M.Sc. (Electronics)
2006-2008
Sardar Patel University
Bachelor of Science - B.Sc. (Electronics)
2003-2006
BPHS, Nadiad
Niraj Jani Skills
ASIC
Physical Design
Partition
Place & Route
Clock Tree Synthesis
Timing Closure
Signal Integrity
Static Timing Analysis
Physical Verification
Power Analysis
Logic Synthesis
Circuit Layout
verilog
Scripting
Awk
TCL
Perl Script
Magma
Synopsys Primetime
ICC
Talus
Encounter
Conformal LEC
Calibre
VHDL
DRC
VLSI
Place And Route
Music
Design
Niraj Jani Summary
Niraj Jani, based in Fremont, CA, US, is currently a Principal ASIC RnD Engineer at Broadcom. Niraj Jani brings experience from previous roles at Juniper Networks, SmartPlay Technologies and eInfochips. Niraj Jani holds a 2006 - 2008 Master of Science - M.Sc. in Electronics @ Sardar Patel University. With a robust skill set that includes ASIC, Physical Design, Partition, Place & Route, Clock Tree Synthesis and more. Niraj Jani has 4 emails and 3 mobile phone numbers on RocketReach.
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