Naveen Meduri's Location
Santa Clara, CA, US
Naveen Meduri's Work
- Sr DFT Methodology Engineer @ NVIDIA
- DFx Engineer @ Intel Corporation
- Mixed Signal Validation Engineer @ Intel Corporation
- Post Silicon Test Engineer @ Intel Corporation
Naveen Meduri's Education
- Southern Illinois University, Carbondale
Master of Science (Electrical & Computer Engineering)
2010 - 2012 - Jawaharlal Nehru Technological University
Bachelor of Technology (Electronics and communications Engineering)
2006 - 2010
Naveen Meduri's Skills
- Verilog
- VLSI
- Debugging
- C
- Analog
- Mixed Signal
- Circuit Design
- Cadence Virtuoso
- VHDL
- CMOS
Naveen Meduri's Summary
Naveen Meduri, based in Santa Clara, CA, US, is currently a Sr DFT Methodology Engineer at NVIDIA, bringing experience from previous roles at Intel Corporation. Naveen Meduri holds a 2010 - 2012 Master of Science in Electrical & Computer Engineering @ Southern Illinois University, Carbondale. With a robust skill set that includes Verilog, VLSI, Debugging, C, Analog and more, Naveen Meduri contributes valuable insights to the industry. Naveen Meduri has 2 emails on RocketReach.
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