Mo Yang Email & Phone Number
Principal Digital ASIC Design Engineer @ Marvell India
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Mo Yang Location
- Santa Clara, CA, US
Mo Yang Work
- Principal Digital ASIC Design Engineer @ (April 2024 - Present)
- Senior Staff Digital ASIC Design Engineer @ (April 2022 - March 2024)
- Staff ASIC Design Engineer @ (February 2019 - March 2022)
- AI ASIC Design Engineer @ (July 2018 - February 2019)
- Research Assistant @ (August 2016 - May 2018)
- Teaching Assistant @ (August 2016 - May 2018)
- Research Assistant @ (February 2013 - July 2016)
- Teaching Assistant @ (September 2014 - May 2015)
- Lab Assistant @ (September 2011 - May 2012)
Mo Yang Education
- Virginia Tech
Master's degree (Computer Engineering)
2016-2018 - University of Rochester
Master's degree (Electrical and Computer Engineering, VLSI, Digital circuit design)
2012-2014 - Nanjing University
Bachelor's degree (Physics)
2008-2012
Mo Yang Skills
- ASIC Verification
- Analog Circuit Design
- C
- C language
- C++
- Cadence
- Cadence tools
- Circuit Design
- Computer Architecture
- EDA
- Embedded Systems
- FPGA
- Field-Programmable Gate Arrays (FPGA)
- High Level Synthesis
- Integrated Circuit Design
- Java
- Linux
- Logic Synthesis
- Low-power Design
- Matlab
- Python
- RTL Design
- Simulations
- Static Timing Analysis
- Synopsys tools
- SystemVerilog
- Verilog
- Xinlinx ISE
Mo Yang Summary
- Mo Yang, based in Santa Clara, CA, US, is currently a Principal Digital ASIC Design Engineer at Marvell Technology. Mo Yang brings experience from previous roles at Marvell Technology, 天数智芯 Iluvatar and Virginia Tech. Mo Yang holds a 2016 - 2018 Master's degree in Computer Engineering @ Virginia Tech. With a robust skill set that includes ASIC Verification, Analog Circuit Design, C, C language, C++ and more. Mo Yang has 1 emails and 1 mobile phone numbers on RocketReach.
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