RF Research Engineer @ Microelectronics' Students Groups (FEUP) - (Cadence Academic Network Contributor
Computer Technician @ Centrocópia de Chaves
Miguel Caetano's Education
Faculty of Engineering of the University of Porto
Final MS.c. Project (Electrical and Computer Engineering (conclusion)
2009 - 2010
Faculdade de Engenharia da Universidade do Porto
MSc (Electrical and Computers Engineering)
2002 - 2010
Lancaster College
English Language Course
2005 - 2006
Escola Secundária Fernão de Magalhães
1996 - 2002
Miguel Caetano's Skills
Integrated Circuit Design
Verilog
FPGA
RTL design
ASIC
Formal Verification
Static Timing Analysis
ModelSim
VLSI
SystemVerilog
Miguel Caetano's Summary
Miguel Caetano, based in Porto, Porto, Portugal, is currently a ASIC Digital Design Engr, Staff at Synopsys Inc, bringing experience from previous roles at Synopsys Inc. Miguel Caetano holds a 2009 - 2010 Final MS.c. Project in Electrical and Computer Engineering (conclusion @ Faculty of Engineering of the University of Porto. With a robust skill set that includes Integrated Circuit Design, Verilog, FPGA, RTL design, ASIC and more, Miguel Caetano contributes valuable insights to the industry. Miguel Caetano has 4 emails and 2 mobile phone numbers on RocketReach.