Michael Ledesma Email
Principal Physical Design Engineer @ Inspire Semiconductor, Inc.
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Michael Ledesma Location
- United States
Michael Ledesma Work
- 2024 -now Principal Physical Design Engineer @
- 2022 -2024 Senior IC Mask Layout Design Engineer @
- 2019 -2022 Senior Mask Layout Designer @
- 2014 -2019 Mask Layout Designer @
Michael Ledesma Education
- Portland Community College
Associate of Science - AS (Website Design & Development)
2015-2021
Michael Ledesma Skills
- High Speed Digital Mask Layout Design
- Cadence Virtuoso
- Floorplanning
- CMOS
- Layout Versus Schematic (LVS)
- Design Rule Checking (DRC)
- IR
- Physical Design
- Cadence Virtuoso Layout Editor
- Low-power Design
- Electromigration
- LINUX/UNIX
- Shell Scripting
- Cross-cultural Communication Skills
- High-speed Digital Design
- Deep SubMicron
- Low-noise Design
- Compiled Memory Structures
- Standard Cell Planning
- Hierarchical Layout Assembly
- RC delay
- Self heating
- Cross Cap
- Calibre RVE
- Calibre DESIGNrev
- Cadence Virtuoso XL and EXL
- Scheduling and Block Management
- Mixed Signal
- Semiconductors
- IC
- Analog
- Analog Circuit Design
- DRC
- LVS
- Integrated Circuit Design
- Digital Circuit Design
- Design Rule Checking Drc
- Layout Versus Schematic Lvs
- Layout Versus Schematic
- Design Rule Checking
Michael Ledesma Summary
- Michael Ledesma, based in United States, is currently a Principal Physical Design Engineer at Inspire Semiconductor, Inc.. Michael Ledesma brings experience from previous roles at Inspire Semiconductor, Inc. and Coast-to-Coast Layout Design, Inc.. Michael Ledesma holds a 2015 - 2021 Associate of Science - AS in Website Design & Development @ Portland Community College. With a robust skill set that includes High Speed Digital Mask Layout Design, Cadence Virtuoso, Floorplanning, CMOS, Layout Versus Schematic (LVS) and more. Michael Ledesma has 2 emails on RocketReach.
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