Meghna Singhal Email & Phone Number
Timing Methodology @ NVIDIA
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Meghna Singhal Location
- California, United States
Meghna Singhal Work
- Timing Methodology @ (July 2024 - Present)
- Physical Design Engineer @ (September 2022 - June 2024)
- Physical Design Engineer @ (August 2021 - September 2022)
- Circuit Design Engineer @ (February 2015 - August 2021)
- Member of Technical Staff @ (January 2009 - January 2015)
- Designer @ (January 2006 - January 2009)
Meghna Singhal Education
- University of Michigan
Master's degree (VLSI)
2004-2006 - Birla Institute of Technology and Science, Pilani
B.Sc (EE)
2000-2004
Meghna Singhal Skills
- VLSI
- Verilog
- Circuit Design
- Microprocessors
- Semiconductors
- SoC
- Design
- Integrated Circuits Ic
- Static Timing Analysis
- Application Specific Integrated Circuits Asic
- Manufacturing
- Integrated Circuit Design
- H Spice
- TCL
- Primetime
- Nanotime
- Perl
- Integrated Circuits
- Application Specific Integrated Circuits
Meghna Singhal Summary
- Meghna Singhal, based in California, United States, is currently a Timing Methodology at NVIDIA. Meghna Singhal brings experience from previous roles at Tesla, Tenstorrent Inc., Apple and AMD. Meghna Singhal holds a 2004 - 2006 Master's degree in VLSI @ University of Michigan. With a robust skill set that includes VLSI, Verilog, Circuit Design, Microprocessors, Semiconductors and more. Meghna Singhal has 3 emails and 1 mobile phone numbers on RocketReach.
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