Mark Rong Email & Phone Number
Principal Physical Design Engineer (Synthesis and Timing) @ Marvell India
5 free lookup(s).
Mark Rong Location
- San Jose, CA, US
Mark Rong Work
- 2021 -now Principal Physical Design Engineer (Synthesis and Timing) @
- 2018 -2021 Sr Staff R and D Engineer @
- 2017 -2018 Physical Design Technical Manager @
- 2013 -2017 Sr Staff Physical Design Engineer @
- 2008 -2013 Place and Route Specialist @
- 2006 -2008 Sr Staff Design Engineer @
- 2002 -2006 Lead Application Engineer @
- 2000 -2002 Application Engineer @ Simplex Solutions
Mark Rong Education
- Northwestern University
Mark Rong Skills
- Physical Design
- Clock Tree Synthesis
- Timing Closure
- Place & Route
- IC
- Timing
- EDA
- ASIC
- SoC
- Static Timing Analysis
- Perl
- Low-power Design
- Physical Verification
- TCL
- Verilog
- Debugging
- System on a Chip (SoC)
- VLSI
- Semiconductors
- LVS
- Low Power Design
- Place And Route
- System On A Chip Soc
- System on a Chip
Mark Rong Summary
- Mark Rong, based in San Jose, CA, US, is currently a Principal Physical Design Engineer (Synthesis and Timing) at Marvell Technology. Mark Rong brings experience from previous roles at Synopsys Inc, TSMC North America, Marvell Semiconductor and Mentor Graphics. Mark Rong holds a Northwestern University. With a robust skill set that includes Physical Design, Clock Tree Synthesis, Timing Closure, Place & Route, IC and more. Mark Rong has 2 emails and 2 mobile phone numbers on RocketReach.
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