2023 -
2025 Design Verification Lead @ Rivos Inc. (acquired by Meta)
2022 -
2023 Principal Member Of Technical Staff @
2018 -
2022 Design Verification Director @ FLC Technology Group
2017 -
2018 Member Of Technical Staff @
2014 -
2017 Design Verification Manager @
2011 -
2014 Staff Verification Engineer @
2005 -
2010 Senior Design Engineer @
Mark Chien Education
University of Michigan
Master of Engineering Science (Electrical Engineering and Computer Science)
2003
-
2005
University of Auckland
Bachelor of Engineering (Computer Engineering)
1999
-
2002
Mark Chien Skills
ARM
Verilog
RTL design
SystemVerilog
ASIC
Microarchitecture
Functional Verification
Logic Design
Perl
Universal Verification Methodology (UVM)
Static Timing Analysis
Shell Scripting
Photoshop
Microsoft Excel
Illustrator
Strategic Planning
Engineering
Universal Verification Methodology Uvm
Universal Verification Methodology
Mark Chien Summary
Mark Chien, based in Dublin, CA, US, is currently a Design Verification Engineer at Meta. Mark Chien brings experience from previous roles at Rivos Inc. (acquired by Meta), FLC Technology Group and InnoGrit Corporation. Mark Chien holds a 2003 - 2005 Master of Engineering Science in Electrical Engineering and Computer Science @ University of Michigan. With a robust skill set that includes ARM, Verilog, RTL design, SystemVerilog, ASIC and more. Mark Chien has 3 emails and 3 mobile phone numbers on RocketReach.
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