2015 -2015 ASIC Design Engineer @ Scalable Systems Research Labs Inc.
2014 -2014 Memory PHY Design @
2013 -2013 Data Engineer, Search Engine Optimization group @
Mandar S. Education
University of Mumbai
Bachelor of Engineering (BEng) (Electrical and Electronics Engineering)
San Jose State University
Mandar S. Skills
Verilog
ModelSim
ASIC
VLSI
FPGA
RTL design
Digital Circuit Design
Integrated Circuit Design
Engineering
Static Timing Analysis
Simulations
Digital IC Design
Perl
Logic Synthesis
C
Microsoft Office
Debugging
Functional Verification
NCSim
Windows
Electrical Engineering
DFT
Logic Design
Computer Architecture
Hardware Architecture
Sound
DDR3
Digital Electronics
Infrastructure
PCIe
Data Structures
Programming
Protocol
Embedded Systems
Leveling
Primetime
Synopsys tools
Design
Si
Assertions
Analyzer
Routing
IC
Linux
Signal
Oscilloscope
Perl Script
Data Validation
UVM
Timing
Xilinx
TCL
Computer Programming
Fedora
Mixed Signal
Nios Ii
Testing
SoC
Scripting
Sdram
Multimeter
SystemVerilog
Complexity Theory
Scan
Component Design
Hardware
Operating Systems
Bluetooth
Characterization
Command
Integrated Circuit
PHY
RTL coding
EDA
Unix
Emulation
Compensation
Logic Analyzer
Function Generator
DDR
Altera Quartus
Cadence Virtuoso
Interfaces
Electronics
Clocking
SIM
Cadence
Test Cases
Analytical Skill
Pattern
OOP
Fundamentals
C++
Synopsys Primetime
Semiconductors
Optimization
AXI
Simulink
Architecture
Virtuoso
Automation
Mandar S. Summary
Mandar S., based in California, United States, is currently a Principal Product Manager at Upscale. Mandar S. brings experience from previous roles at Cisco and Intel Corporation. Mandar S. holds a Bachelor of Engineering (BEng) in Electrical and Electronics Engineering @ University of Mumbai. With a robust skill set that includes Verilog, ModelSim, ASIC, VLSI, FPGA and more. Mandar S. has 1 emails and 2 mobile phone numbers on RocketReach.
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