Dharmendra Patel's Location
Santa Clara, CA, US
Dharmendra Patel's Work
- Sr. Principal Engineer - ASIC Verification @ Auradine
- Sr. Manager - ASIC Verification @ Palo Alto Networks
- Sr. Principal Engineer - ASIC Verification @ Palo Alto Networks
- Principal Engineer - ASIC Verification @ Palo Alto Networks
- Sr. Staff Engineer - ASIC Verification @ Palo Alto Networks
- Staff Engineer - ASIC Verification @ Palo Alto Networks
- Verification Engineer @ Altera
- Senior Member of Technical Staff @ Aquantia
- ASIC engineer @ eInfochips (An Arrow Company)
- Lecturer @ Nirma University, Ahmedabad, Gujarat, India
Dharmendra Patel's Education
(Vlsi Design)
2001 - 2002- South Gujarat University
(Electronics)
1997 - 2001
Dharmendra Patel's Skills
- SystemVerilog
- Higher Education
- SoC
- Specman
- Qualitative Research
Dharmendra Patel's Summary
Dharmendra Patel, based in Santa Clara, CA, US, is currently a Sr. Principal Engineer - ASIC Verification at Auradine, bringing experience from previous roles at Palo Alto Networks. Dharmendra Patel holds a 2001 - 2002 . With a robust skill set that includes SystemVerilog, Higher Education, SoC, Specman, Qualitative Research and more, Dharmendra Patel contributes valuable insights to the industry. Dharmendra Patel has 3 emails on RocketReach.
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