Mac Lin Email & Phone Number
ASIC design verification-LPU @ NVIDIA
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Mac Lin Location
- San Jose, CA, US
Mac Lin Work
- 2026 -now ASIC design verification-LPU @
- 2024 -2026 ASIC MTS - ASIC Design Verification @
- 2022 -2024 Principal Design Verification Engineer, SoC DV Lead @
- 2020 -2022 Principal Engineer, Global Verification Team Lead, Manager @
- 2018 -2020 Staff Design Verification Engineer @
- 2016 -2018 Senior Design Verification Engineer @
- 2012 -2016 Design Verification Engineer @
- 2011 -2012 Logic Design Engineer @ Grace Semiconductor Manufacturing Corporation
Mac Lin Education
- Fudan University
Master's degree (Integrated Circuits and Systems)
- Xiangtan University
Bachelor's degree (Microelectronics)
Mac Lin Skills
- Static Timing Analysis
- RTL design
- EDA
- Logic Design
- Logic Synthesis
- Functional Verification
Mac Lin Summary
- Mac Lin, based in San Jose, CA, US, is currently a ASIC design verification-LPU at NVIDIA. Mac Lin brings experience from previous roles at Micron Technology and 美光科技. Mac Lin holds a Master's degree in Integrated Circuits and Systems @ Fudan University. With a robust skill set that includes Static Timing Analysis, RTL design, EDA, Logic Design, Logic Synthesis and more. Mac Lin has 2 emails and 2 mobile phone numbers on RocketReach.
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