Louis Phan Email & Phone Number
Sr. Physical Design Manager @ Marvell India
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Louis Phan Location
- San Jose, CA, US
Louis Phan Work
- Sr. Physical Design Manager @ (February 2002 - Present)
- Staff Design Engineer @ (January 2000 - February 2002)
- Senior Design Engineer @ Philips Semiconductor (June 1999 - December 1999)
- Design Engineer @ VLSI Technology (June 1994 - December 1999)
Louis Phan Skills
- ASIC
- Physical Design
- EDA
- Floorplanning
- SoC
- Timing Closure
- IC
- Low-power Design
- VLSI
- CMOS
- Semiconductors
- Static Timing Analysis
- Integrated Circuit Design
- Verilog
- Application-Specific Integrated Circuits (ASIC)
- Customer Service
- Application Specific Integrated Circuits Asic
- Microsoft Word
- Sales
- Software Development
- InDesign
- Low Power Design
- Application Specific Integrated Circuits
Louis Phan Summary
- Louis Phan, based in San Jose, CA, US, is currently a Sr. Physical Design Manager at Marvell Semiconductor. Louis Phan brings experience from previous roles at LSI Corporation, Philips Semiconductor and VLSI Technology. With a robust skill set that includes ASIC, Physical Design, EDA, Floorplanning, SoC and more. Louis Phan has 1 emails and 2 mobile phone numbers on RocketReach.
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