Loic Vezier Email
SoC Architect @ Silicon Mobility
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Loic Vezier Location
- Nice, FR
Loic Vezier Work
- Senior SoC and FPGA Design Engineer @ Scaleo chip (May 2004 - December 2015)
- SoC Architect @ (December 2022 - Present)
- AxEC and FPGA and Tools Technical Lead @ (December 2015 - December 2022)
- Ingénieur en micro-électronique @ (November 2001 - April 2004)
Loic Vezier Education
- lSIMA Clermont-Ferrand
Ingénieur en informatique des systèmes embarqués (Informatique des Systèmes Embarqués)
1998-2001 - Lycée Pierre Corneille - Rouen
Classes péparatoires PSI*
1996-1998
Loic Vezier Skills
- ARM
- Altera Quartus
- AXI
- Microsoft Office
- Timing Analysis
- System Testing
- Perl Script
- AMBA AHB
- Architecture Arm
- Altera
- FPGA
- Arm Cortex R5
- ModelSim
- Embedded Software
- Embedded Systems
- Altera Qsys
- Ethernet IP
- Semi Conducteur
- Strategic Planning
- Synplify Pro
- Perl
- FPGA prototyping
- Simulations
- VHDL
- Numerical Simulation
- Project Management
- RTL design
- DDR2
- ASIC
- SoC
- Verilog
- Manufacturing
- Arm Cortex M3
- Apb
Loic Vezier Summary
- Loic Vezier, based in Nice, FR, is currently a SoC Architect at Silicon Mobility. Loic Vezier brings experience from previous roles at Arteris, Scaleo chip, Silicon Mobility and Actsoft. Loic Vezier holds a 1998 - 2001 Ingénieur en informatique des systèmes embarqués in Informatique des Systèmes Embarqués @ lSIMA Clermont-Ferrand. With a robust skill set that includes ARM, Altera Quartus, AXI, Microsoft Office, Timing Analysis and more. Loic Vezier has 1 emails on RocketReach.
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