Laszlo Borbely Email & Phone Number
Sr. Principal Design Engineer @ Cadence Design Systems
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Laszlo Borbely Location
- San Jose, CA, US
Laszlo Borbely Work
- 2017 -now Sr. Principal Design Engineer @
- 2017 -now Senior Principal Design Engineer @
- 2011 -2016 Senior Staff Design Engineer @
- 2007 -2011 Staff Design Engineer @
- 2003 -2007 Senior Design Engineer @
- 2000 -2003 Design Engineer @
- 1998 -2000 Application Engineer @
- 1998 -2000 Application Engineer @ Integrated Technology Group/Rendition
- 1998 -1998 Application Engineer @ Rendition
- 1997 -1998 Application Engineer @ ARK Logic
- 1995 -1996 System Engineer @ PADSystems
Laszlo Borbely Education
- Stanford Continuing Studies
(Algebraic Codes for Error Correction)
2007-2007 - UCSC Silicon Valley Extension
(Bridges and Routers: Algorithms and Protocols)
2003-2003 - UCSC Silicon Valley Extension
(Digital Design Using Verilog)
1999-1999 - UCSC Silicon Valley Extension
(Computer Graphics: Principles and Practices)
1998-1998 - UCSC Silicon Valley Extension
(Microsoft Windows Application Programming)
1997-1997 - Universitatea Tehnică din Cluj-Napoca
Master's degree (Electrical and Electronics Engineering)
- Universitatea Tehnică din Cluj-Napoca
M.S.E.E. (Electrical and Electronics Engineering)
Laszlo Borbely Skills
- Flash Memory
- NCSim
- Debugging
- Logic Design
- Semiconductors
- RTL coding
- ARM
- RTL design
- Functional Verification
- USB
- SoC
- IC
- DFT
- Semiconductor Industry
- Primetime
- ASIC
- Static Timing Analysis
- SystemVerilog
- Embedded Systems
- Verilog
- VLSI
- System on a Chip (SoC)
- Application-Specific Integrated Circuits (ASIC)
- Integrated Circuits (IC)
- ARM Architecture
- Field-Programmable Gate Arrays (FPGA)
- Simulations
- Field Programmable Gate Arrays Fpga
- System On A Chip Soc
- Integrated Circuits Ic
- Application Specific Integrated Circuits Asic
- System on a Chip
- Application Specific Integrated Circuits
- Integrated Circuits
- Field Programmable Gate Arrays
Laszlo Borbely Summary
- Laszlo Borbely, based in San Jose, CA, US, is currently a Sr. Principal Design Engineer at Cadence Design Systems. Laszlo Borbely brings experience from previous roles at Cadence Design Systems and Micron Technology. Laszlo Borbely holds a 2007 - 2007 Stanford Continuing Studies. With a robust skill set that includes Flash Memory, NCSim, Debugging, Logic Design, Semiconductors and more. Laszlo Borbely has 3 emails and 3 mobile phone numbers on RocketReach.
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