Kritika B. Email
Physical Design Engineer @ Broadcom
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Kritika B. Location
- Santa Clara, CA, US
Kritika B. Work
- Physical Design Engineer @ (August 2024 - Present)
- Principal Application Engineer @ (January 2024 - August 2024)
- Senior CPU Physical Design Engineer @ (September 2022 - December 2023)
- Physical Design Engineer @ (July 2017 - July 2022)
- Intern @ (January 2017 - July 2017)
- Engineering Student @ (August 2013 - December 2016)
- Embedded intern @ Centre for the Development of Advanced Computing (CDAC) (June 2015 - July 2015)
Kritika B. Education
- Thapar Institute of Engineering & Technology
B.E. (Electronics and communication engineering)
2013-2017
Kritika B. Skills
- AVR Studio 4
- Assembly Language
- C
- CST Microwave Studio
- CTS
- Clock Tree Synthesis
- Design compiler
- ECO
- EDA tools: Synopsys (DC,DCT,ICC1,ICC2,FC,PT) & Cadence (Genus,Innovus)
- Embedded Systems
- Floorplanning
- Logic Synthesis
- Low-power Design
- Matlab
- PDN
- PNR
- Physical Design
- Place & Route
- RTL to GDS
- Raspberry Pi
- Static Timing Analysis
- Synopsys IC Compiler
- Synopsys tools
- Synthesis
- System on a Chip (SoC)
- TCL
- UPF
- VHDL
- keil uvision
- primetime
- vlsi design flow
Kritika B. Summary
- Kritika B., based in Santa Clara, CA, US, is currently a Physical Design Engineer at Broadcom. Kritika B. brings experience from previous roles at Cadence Design Systems, SiFive and Intel Corporation. Kritika B. holds a 2013 - 2017 B.E. in Electronics and communication engineering @ Thapar Institute of Engineering & Technology. With a robust skill set that includes AVR Studio 4, Assembly Language, C, CST Microwave Studio, CTS and more. Kritika B. has 1 emails on RocketReach.
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