Konark Patel Email & Phone Number
Physical Design and Timing @ NVIDIA
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Konark Patel Location
- Cary, NC, US
Konark Patel Work
- Physical Design and Timing @ (September 2023 - Present)
- Principal Physical Design Engineer @ (May 2022 - September 2023)
- Senior Hardware Design Engineer @ (August 2018 - May 2022)
- Advanced CPU Design @ Qualcomm (July 2013 - August 2018)
- Circuit Design Engineer @ (May 2008 - July 2013)
- Hardware Engineer @ (January 2007 - May 2008)
- Circuit Design Engineer (coop) @ (January 2006 - January 2007)
- Bluetooth verification coop @ (January 2006 - January 2006)
Konark Patel Education
- North Carolina State University 2005-2006
- North Gujarat University 2000-2004
Konark Patel Skills
- Timing constraints
- Scripting
- Python (Programming Language)
- DFT Timing
- STA Constraints
- Circuit Design
- Circuit Analysis
- Digital Circuit Design
- Integrated Circuit Design
- VLSI
- Static Timing Analysis
- Timing Closure
- Perl Script
- VHDL
- Verilog
- Cadence
- ASIC
- Debugging
- IC
- EDA
- Matlab
- Embedded Systems
- Logic Design
- Processors
- TCL
- Computer Architecture
- Hardware
Konark Patel Summary
- Konark Patel, based in Cary, NC, US, is currently a Physical Design and Timing at NVIDIA. Konark Patel brings experience from previous roles at Microsoft, Qualcomm and IBM. Konark Patel holds a 2005 - 2006 North Carolina State University. With a robust skill set that includes Timing constraints, Scripting, Python (Programming Language), DFT Timing, STA Constraints and more. Konark Patel has 2 emails and 2 mobile phone numbers on RocketReach.
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