Kartik K's Location
California, United States
Kartik K's Work
- Principal DDR verification Engineer @ Cadence Design Systems
- DDR Lead verification Engineer @ Cadence Design Systems
- DDR Verification Engineer @ Cadence Design Systems
- Multi Core Simulation Engineer. @ Cadence Design Systems
- Software Intern @ Cadence Design Systems
- Lecturer @ R N Shetty Polytechnic
Kartik K's Education
- San Jose State University
Master’s Degree (Electrical, Electronics and Communications Engineering)
2015 - 2017 - S G Balekundari Institute of Technology
Bachelor’s Degree (Electrical, Electronics and Communications Engineering)
2010 - 2014 - St Xavier High School
High School (English)
1997 - 2008
Kartik K's Skills
- Leadership
- PowerPoint
- Linux
- C
- System Verilog
- Perl
- Matlab
- UVM
- ASIC
- Verilog
Kartik K's Summary
Kartik K, based in California, United States, is currently a Principal DDR verification Engineer at Cadence Design Systems, bringing experience from previous roles at Cadence Design Systems. Kartik K holds a 2015 - 2017 Master’s Degree in Electrical, Electronics and Communications Engineering @ San Jose State University. With a robust skill set that includes Leadership, PowerPoint, Linux, C, System Verilog and more, Kartik K contributes valuable insights to the industry. Kartik K has 1 email on RocketReach.
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