Karthikeya Palepu's Location

San Jose, CA, US

Karthikeya Palepu's Work

  • Intern-R&D Electrical Engineering. @ Covidien

Karthikeya Palepu's Education

  • Arizona State University

    Master's Degree (Computer Engineering)

    2012 - 2014
  • Jawaharlal Nehru Technological University

    Bachelor of Technology (BTech) (Electrical, Electronics and Communications Engineering)

    2008 - 2012
  • St.Patricks High School

    High School Graduate (93)

    1994 - 2006

Karthikeya Palepu's Skills

  • VHDL
  • Matlab
  • Verilog
  • C
  • Xilinx
  • Cadence
  • FPGA
  • Functional Verification
  • Java
  • Microsoft Office

Karthikeya Palepu's Summary

Karthikeya Palepu, based in San Jose, CA, US, is currently a MTS Silicon Design Engineer at AMD, bringing experience from previous roles at AMD, Micron Technology and Covidien. Karthikeya Palepu holds a 2012 - 2014 Master's Degree in Computer Engineering @ Arizona State University. With a robust skill set that includes VHDL, Matlab, Verilog, C, Xilinx and more, Karthikeya Palepu contributes valuable insights to the industry. Karthikeya Palepu has 2 emails on RocketReach.

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