Kamesh P Email
Senior Design Engineer @ NVIDIA
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Kamesh P Location
- Visakhapatnam, AP, IN
Kamesh P Work
- Senior Design Engineer @ (May 2024 - Present)
- Soc Lead @ (April 2022 - May 2024)
- P1 Technical Architect of Physical Design @ (May 2018 - June 2022)
- Senior Design Engineer @ (May 2013 - April 2018)
- Physical Design Engineer @ Infotech Enterprises Ltd (December 2010 - April 2013)
Kamesh P Education
- Andhra University
Master of Technology - MTech (VLSI)
2012-2014 - JNTU University
B.Tech (Electronics and communication engg)
2006-2010 - Narayana College
Intermediate (MPC)
2004-2006 - MNR High School
SSC (all)
2002-2004 - St. Alyosius Anglo Indian High School 1993-2002
Kamesh P Skills
- VLSI
- ASIC
- CMOS
- VHDL
- Semiconductors
- Static Timing Analysis
- Physical Design
- Timing Closure
- Floorplanning
- Place & Route
- Primetime
- TCL
- LVS
- DRC
- Cadence
- Debugging
- Design
- Place And Route
Kamesh P Summary
- Kamesh P, based in Visakhapatnam, AP, IN, is currently a Senior Design Engineer at NVIDIA. Kamesh P brings experience from previous roles at Intel Corporation, Cerium Systems, AMD and Infotech Enterprises Ltd. Kamesh P holds a 2012 - 2014 Master of Technology - MTech in VLSI @ Andhra University. With a robust skill set that includes VLSI, ASIC, CMOS, VHDL, Semiconductors and more. Kamesh P has 1 emails on RocketReach.
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