Kai-Wei Lin Email
ASIC Power Architect Engineer @ NVIDIA
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Kai-Wei Lin Location
- Mountain View, CA, US
Kai-Wei Lin Work
- ASIC Power Architect Engineer @ (July 2024 - Present)
- Military Service @ (June 2023 - July 2023)
- Undergraduate Researcher @ (September 2021 - June 2023)
- Undergraduate Researcher @ (July 2020 - August 2020)
Kai-Wei Lin Education
- University of California, Berkeley
Master of Engineering - MEng (Electrical Engineering and Computer Science)
2023-2024 - National Taiwan University
Bachelor of Science - BS (Engineering Science and Ocean Engineering)
2019-2023 - Taipei Municipal Jianguo High School 2016-2019
Kai-Wei Lin Skills
- Application-Specific Integrated Circuits (ASIC)
- Integrated Circuits (IC)
- VLSI Testing
- Automatic Test Pattern Generation (ATPG)
- Test Compression
- Testability Measure
- Finite State Machines
- Algorithm
- APR
- Java
- LabVIEW
- Digital IC Design
- Very-Large-Scale Integration (VLSI)
- Matlab
- Verilog
- C++
- Computer Architecture
- RISC-V
- Field-Programmable Gate Arrays (FPGA)
- PSpice
- Power Devices
- Digital IC Design · Very-Large-Scale Integration (VLSI) · Field-Programmable Gate Arrays (FPGA)
- Microsoft PowerPoint
- 簡報
- 領導力
- 英文
Kai-Wei Lin Summary
- Kai-Wei Lin, based in Mountain View, CA, US, is currently a ASIC Power Architect Engineer at NVIDIA. Kai-Wei Lin brings experience from previous roles at ROC Army (Taiwan) and 國立台灣大學. Kai-Wei Lin holds a 2023 - 2024 Master of Engineering - MEng in Electrical Engineering and Computer Science @ University of California, Berkeley. With a robust skill set that includes Application-Specific Integrated Circuits (ASIC), Integrated Circuits (IC), VLSI Testing, Automatic Test Pattern Generation (ATPG), Test Compression and more. Kai-Wei Lin has 1 emails on RocketReach.
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