Jyotsna M Email
Senior ASIC Design Engineer @ NVIDIA
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Jyotsna M Location
- Bengaluru, KA, IN
Jyotsna M Work
- Senior ASIC Design Engineer @ (March 2026 - Present)
- ASIC Design Engineer @ (July 2024 - April 2026)
- Engineer @ (December 2023 - July 2024)
- Associate Engineer @ (June 2022 - November 2023)
- Executive Member @ (August 2019 - August 2022)
- Hardware Engineering Intern @ (April 2021 - July 2021)
- Aradhana Event Co-ordinator @ (December 2019 - January 2020)
Jyotsna M Education
- National Institute of Technology Karnataka
Bachelor of Technology - BTech (Electronics and Communications Engineering)
2018-2022 - VVS Sardar Patel PU College 2016-2017
- Cluny Convent High School - India
Jyotsna M Summary
- Jyotsna M, based in Bengaluru, KA, IN, is currently a Senior ASIC Design Engineer at NVIDIA. Jyotsna M brings experience from previous roles at NVIDIA, Qualcomm and IEEE NITK. Jyotsna M holds a 2018 - 2022 Bachelor of Technology - BTech in Electronics and Communications Engineering @ National Institute of Technology Karnataka. Jyotsna M has 1 emails on RocketReach.
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