Jyotsna M Email
Senior ASIC Design Engineer @ NVIDIA
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Jyotsna M Location
- Bengaluru, KA, IN
Jyotsna M Work
- 2026 -now Senior ASIC Design Engineer @
- 2024 -2026 ASIC Design Engineer @
- 2023 -2024 Engineer @
- 2022 -2023 Associate Engineer @
- 2019 -2022 Executive Member @
- 2021 -2021 Hardware Engineering Intern @
- 2019 -2020 Aradhana Event Co-ordinator @
Jyotsna M Education
- National Institute of Technology Karnataka
Bachelor of Technology - BTech (Electronics and Communications Engineering)
2018-2022 - VVS Sardar Patel PU College 2016-2017
- Cluny Convent High School - India
Jyotsna M Summary
- Jyotsna M, based in Bengaluru, KA, IN, is currently a Senior ASIC Design Engineer at NVIDIA. Jyotsna M brings experience from previous roles at NVIDIA, Qualcomm and IEEE NITK. Jyotsna M holds a 2018 - 2022 Bachelor of Technology - BTech in Electronics and Communications Engineering @ National Institute of Technology Karnataka. Jyotsna M has 1 emails on RocketReach.
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