Jonathan Choy Location
- California, United States
Jonathan Choy Work
- 2014 - now Senior IP Design Engineer - Pixel IP @
- 2008 - 2014 ASIC Design Engineer - CPU Implementation and PD @
- 2003 - 2008 Sr Design Engineer @
- 2000 - 2001 CAD Co-op and Intern Engineer @
Jonathan Choy Education
- University of California, Berkeley
Master of Science (MS) (Electrical Engineering)
2001 - 2003 - University of California, Berkeley
Bachelor of Science (BS) (Electrical Engineering and Computer Sciences)
1997 - 2001
Jonathan Choy Skills
- IC
- Microprocessors
- Timing Closure
- Logic Design
- Silicon
- ASIC
- SoC
- Verilog
- Engineering
- Static Timing Analysis
- RTL design
- Semiconductors
- Integrated Circuit Design
- Low-power Design
- TCL
- Power
- Computer Hardware
- IPS
- Application Specific Integrated Circuits Asic
- Design
- Physical Design
- Low Power Design
- Integration
- Application Specific Integrated Circuits
Jonathan Choy Summary
- Jonathan Choy, based in California, United States, is currently a Senior IP Design Engineer - Pixel IP at Apple. Jonathan Choy brings experience from previous roles at Apple and Advanced Micro Devices. Jonathan Choy holds a 2001 - 2003 Master of Science (MS) in Electrical Engineering @ University of California, Berkeley. With a robust skill set that includes IC, Microprocessors, Timing Closure, Logic Design, Silicon and more. Jonathan Choy has 2 emails and 3 mobile phone numbers on RocketReach.
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