Joe Canning Email
Senior Principal Design Engineer @ Cadence Design Systems
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Joe Canning Location
- Cork, IE
Joe Canning Work
- Senior Principal Design Engineer @ (January 2026 - Present)
- Senior Principal Application Engineer @ (December 2020 - December 2025)
- Linear Precision Staff Engineer @ (January 2012 - October 2020)
- Automotive Sensor Staff Digital Design Engineer @ (January 2009 - December 2011)
- Project Manager and Video Staff Digital Design Engineer @ (June 2001 - December 2008)
- Senior Video Test Development Engineer and Group Leader @ (January 1993 - May 2001)
- Mixed Signal Test Development Engineer @ (August 1987 - December 1992)
- Summer Intern (Co-op) @ (June 1986 - September 1986)
Joe Canning Education
- University College Dublin
BE 1st Class Honours (Electronic Engineering)
Joe Canning Skills
- ASIC
- ATPG
- Analog
- CMOS
- Cadence Incisive
- Cadence Xcelium
- Circuit Design
- DAC
- DFT
- DSP
- Debugging
- Digital Design
- Digital Electronics
- Digital Signal Processors
- Electronics
- Field-Programmable Gate Arrays (FPGA)
- Hardware Architecture
- Hardware Design
- I2C
- IC
- ICS
- Integrated Circuit Design
- Labview
- Matlab
- Microelectronics
- Mixed Signal
- NCSim
- PCB design
- Primetime
- Project Management
- RTL Design
- RTL coding
- SPI
- Semiconductor Design
- Semiconductor Industry
- Semiconductors
- Sensors
- Silicon Debug
- Simulation
- Simulations
- Static Timing Analysis
- Test Engineering
- Timing Closure
- Verilog
Joe Canning Summary
- Joe Canning, based in Cork, IE, is currently a Senior Principal Design Engineer at Cadence. Joe Canning brings experience from previous roles at Cadence and Analog Devices. Joe Canning holds a BE 1st Class Honours in Electronic Engineering @ University College Dublin. With a robust skill set that includes ASIC, ATPG, Analog, CMOS, Cadence Incisive and more. Joe Canning has 1 emails on RocketReach.
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