Joe Berman Email & Phone Number
ASIC Hardware Engineering Director @ NVIDIA
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Joe Berman Location
- San Francisco, CA, US
Joe Berman Work
- ASIC Hardware Engineering Director @ (April 2026 - Present)
- ASIC Hardware Engineering Manager @ (July 2021 - May 2026)
- Senior ASIC Efficiency Engineer @ (August 2013 - July 2021)
- Graduate Pre-Silicon Validation Intern @ (May 2012 - August 2012)
- Software Engineering Choice Intern @ (May 2011 - July 2011)
- College Student Senior Technical Intern @ (June 2010 - July 2010)
- System Administration Fellow @ (June 2009 - January 2010)
- Help Desk Assistant @ (June 2008 - July 2008)
Joe Berman Education
- Carnegie Mellon University
Master's of Science (Master's of Science, Electrical and Computer Engineering)
2011-2012 - Carnegie Mellon University
Bachelor's of Science (Bachelor's of Science, Electrical and Computer Engineering)
2008-2011
Joe Berman Skills
- RTL design
- Computer Architecture
- Pre-Silicon Validation
- FPGA
- Systems Programming
- Software Engineering
- SystemVerilog
- Verilog
- x86 Assembly
- Simulations
- ASIC
- Logic Design
- Device Drivers
- Microcontrollers
- Embedded Systems
- ModelSim
- C++
- Performance
- Pre Silicon Validation
- Computer Hardware
Joe Berman Summary
- Joe Berman, based in San Francisco, CA, US, is currently a ASIC Hardware Engineering Director at NVIDIA. Joe Berman brings experience from previous roles at NVIDIA, Intel Corporation and Cisco Systems. Joe Berman holds a 2011 - 2012 Master's of Science in Master's of Science, Electrical and Computer Engineering @ Carnegie Mellon University. With a robust skill set that includes RTL design, Computer Architecture, Pre-Silicon Validation, FPGA, Systems Programming and more. Joe Berman has 2 emails and 1 mobile phone numbers on RocketReach.
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