Jing Fu Email
ASIC Digital Design, Principal Engineer @ Synopsys Inc
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Jing Fu Location
- Ottawa, ON, CA
Jing Fu Work
- 2020 -now ASIC Digital Design, Principal Engineer @
- 2016 -now Senior Staff Verification Engineer @
- 2013 -2015 Senior Verification Lead @
- 2010 -2013 Staff Verification Engineer @
- 2008 -2010 Senior Verification Lead @
- 2002 -2007 Senior Verification Engineer @ PMC-Sierra Corporation
- 2000 -2002 Senior Verification Engineer @ Extreme Packet Devices Inc. / PMC-Sierra Inc
- 1999 -2000 Senior Verification Engineer @ Extreme Packet Devices (Acquired by PMC-Sierra)
- 1997 -1999 FPGA and ASIC Designer @ Nortel Networks
Jing Fu Education
- Carleton University
E (Eletrical Engineering)
1992-1997
Jing Fu Skills
- Hardware Architecture
- Field Programmable Gate Arrays Fpga
- Debugging
- System On A Chip Soc
- Functional Verification
- RTL design
- PCIe
- UVM
- ASIC
- VMM
- Verilog
- Integrated Circuits Ic
- Embedded Systems
- Application Specific Integrated Circuits Asic
- FPGA
- SoC
- Open Verification Methodology
- Vera
- VHDL
- Universal Verification Methodology Uvm
- SystemVerilog
- Semiconductors
- IC
- System on a Chip
- Universal Verification Methodology
- Integrated Circuits
- Application Specific Integrated Circuits
- Field Programmable Gate Arrays
Jing Fu Summary
- Jing Fu, based in Ottawa, ON, CA, is currently a ASIC Digital Design, Principal Engineer at Synopsys Inc. Jing Fu brings experience from previous roles at Xilinx, Coveloz Consulting Ltd., IDT Canada Inc. and Flextronics. Jing Fu holds a 1992 - 1997 E in Eletrical Engineering @ Carleton University. With a robust skill set that includes Hardware Architecture, Field Programmable Gate Arrays Fpga, Debugging, System On A Chip Soc, Functional Verification and more. Jing Fu has 3 emails on RocketReach.
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