Jin Liang's Location
Saratoga, CA, US
Jin Liang's Work
- Senior Principal Engineer @ Cadence Design Systems
- Physical Design Engineer @ Intel Corporation
- Senior Principle Engineer @ Cadence Design Systems
- Staff Engineer Place and Route @ Siemens
- Sr. Sales Technical Lead @ Cadence Design Systems
- ASIC Physical Design Engineer @ PMC-Sierra is now Microsemi
- Application Consultant @ Synopsys Inc
- Application Engineer @ Avanti
Jin Liang's Education
- Shanghai Jiao Tong University
Bachelor’s Degree
- University of Wyoming
Master’s Degree
Jin Liang's Skills
- Semiconductors
- Mixed Signal
- ASIC
- Static Timing Analysis
- SoC
- Verilog
- VLSI
- EDA
- Debugging
- TCL
Jin Liang's Summary
Jin Liang, based in Saratoga, CA, US, is currently a Senior Principal Engineer at Cadence Design Systems, bringing experience from previous roles at Intel Corporation, Cadence Design Systems and Siemens EDA (Siemens Digital Industries Software). Jin Liang holds a Bachelor’s Degree @ Shanghai Jiao Tong University. With a robust skill set that includes Semiconductors, Mixed Signal, ASIC, Static Timing Analysis, SoC and more, Jin Liang contributes valuable insights to the industry. Jin Liang has 2 emails on RocketReach.
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