Jayesh Patil Email & Phone Number
Hardware Validation Engineer @ Astera Labs
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Jayesh Patil Location
- San Jose, CA, US
Jayesh Patil Work
- Hardware Validation Engineer @ (July 2024 - Present)
- Serdes System Valdation Engineer @ (May 2017 - July 2024)
- Senior Design Engineer @ (January 2011 - January 2017)
- Analog Design Engineer @ (January 2010 - January 2011)
Jayesh Patil Education
- Stanford University
Graduate Certificate (Analog IC Design)
- San José State University
MSEE
- University of Mumbai
BSEE
Jayesh Patil Skills
- ASIC
- Analog
- Analog Circuit Design
- Application-Specific Integrated Circuits (ASIC)
- CDRs
- Field-Programmable Gate Arrays (FPGA)
- IC
- Integrated Circuit Design
- Integrated Circuits (IC)
- Mixed Signal
- PLL
- Phase-Locked Loop (PLL)
- Power Management
- SERDES
- Semiconductors
- Signal Integrity
- SoC
- Systems Engineering
- Testing
- VLSI
- Verilog
- Very-Large-Scale Integration (VLSI)
- Wireless
- Integrated Circuits Ic
- Application Specific Integrated Circuits Asic
- Very Large Scale Integration Vlsi
- Phase Locked Loop Pll
- Phase Locked Loop
- Application Specific Integrated Circuits
- Very Large Scale Integration
- Integrated Circuits
Jayesh Patil Summary
- Jayesh Patil, based in San Jose, CA, US, is currently a Hardware Validation Engineer at Astera Labs. Jayesh Patil brings experience from previous roles at Cadence Design Systems, Xilinx and Arasan Chip Systems Inc.,. Jayesh Patil holds a Graduate Certificate in Analog IC Design @ Stanford University. With a robust skill set that includes ASIC, Analog, Analog Circuit Design, Application-Specific Integrated Circuits (ASIC), CDRs and more. Jayesh Patil has 2 emails and 3 mobile phone numbers on RocketReach.
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