Jayesh Patil Location
San Jose, CA, US
Jayesh Patil Work
- 2024 - now Hardware Validation Engineer @ Astera Labs
- 2017 - 2024 Serdes System Valdation Engineer @ Cadence Design Systems
- 2011 - 2017 Senior Design Engineer @ Xilinx
- 2010 - 2011 Analog Design Engineer @ Arasan Chip Systems Inc.
Jayesh Patil Education
- Stanford University
Graduate Certificate, Analog IC Design
- San José State University
MSEE, Analog & Mixed Signal Design
- University of Mumbai
BSEE, Electronics and Communications Engineering
Jayesh Patil Skills
- Signal Integrity
- Systems Engineering
- Analog Circuit Design
- Cdrs
- Analog
- ASIC
- Power Management
- VLSI
- Verilog
- Integrated Circuit Design
Jayesh Patil Summary
Jayesh Patil, based in San Jose, CA, US, is currently a Hardware Validation Engineer at Astera Labs. Jayesh Patil brings experience from previous roles at Cadence Design Systems, Xilinx and Arasan Chip Systems Inc.,. Jayesh Patil holds a Graduate Certificate, Analog IC Design @ Stanford University. With a robust skill set that includes Signal Integrity, Systems Engineering, Analog Circuit Design, Cdrs, Analog and more. Jayesh Patil has 2 emails and 3 mobile phone numbers on RocketReach.
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Top Astera Labs Employees
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