Jayesh Pandey Email & Phone Number
Senior Methodology Engineer (DFT) @ NVIDIA
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Jayesh Pandey Location
- Santa Clara, CA, US
Jayesh Pandey Work
- Senior Methodology Engineer (DFT) @ (March 2016 - Present)
- Staff, Engineer @ Tech Vulcan (Client Qualcomm) (July 2015 - January 2016)
- Technical Lead @ (June 2014 - June 2015)
- Sr. Design Engineer (DFT) @ (August 2012 - April 2014)
- Sr. Design Engineer Methodology @ LSI Corporation (June 2010 - July 2012)
- Design Engineer - DFT @ (September 2006 - December 2009)
Jayesh Pandey Education
- ABV-Indian Institute of Information Technology and Management
M.Tech. (VLSI-Design)
- NIT Hamirpur (H.P.)
B.Tech. (EE)
Jayesh Pandey Summary
- Jayesh Pandey, based in Santa Clara, CA, US, is currently a Senior Methodology Engineer (DFT) at NVIDIA. Jayesh Pandey brings experience from previous roles at Tech Vulcan (Client Qualcomm), eInfochips, Texas Instruments and LSI Corporation. Jayesh Pandey holds a M.Tech. in VLSI-Design @ ABV-Indian Institute of Information Technology and Management. Jayesh Pandey has 3 emails and 3 mobile phone numbers on RocketReach.
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