Jayasurya B. Email & Phone Number
Senior Mask Design Engineer @ NVIDIA
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Jayasurya B. Location
- Santa Clara, CA, US
Jayasurya B. Work
- Senior Mask Design Engineer @ (March 2025 - Present)
- Senior Analog and Mixed-Signal Layout Engineer @ (January 2022 - March 2025)
- Analog and Mixed Signal IC Layout Design Engineer @ (November 2019 - December 2021)
- IC Layout Engineer @ (June 2018 - August 2019)
- Graduate Teaching Assistant @ (August 2018 - December 2018)
- Intern @ EASY ARM (May 2016 - June 2016)
Jayasurya B. Education
- Southern Illinois University Edwardsville 2017-2019
- GITAM Deemed University 2013-2017
Jayasurya B. Skills
- Physical Verification
- ERC
- ESD
- Self Heating
- Analog-to-Digital Converters (ADC)
- Phase-Locked Loop (PLL)
- SerDes
- Mask Layout
- RXFE
- Current Mirrors
- Calibre
- Debugging
- Front-End Development
- Self-Motivation
- Layout Tools
- Analog Layout
- Cadence Virtuoso
- Analog Circuits
- Layout Design
- Very-Large-Scale Integration (VLSI)
- Analog Circuit Design
- Mixed Signal
- Circuit Design
- Semiconductors
- Scripting
- Integrated Circuits (IC)
- Matlab
- Verilog
- Python
- C (Programming Language)
- LTSpice
- Cadence Virtuoso Layout Editor
- Xilinx
- Xilinx ISE
- Integrated Circuit Design
- Verilog-A
- IC Layout
- Design Rule Checking (DRC)
- Layout Versus Schematic (LVS)
- TCL
- Mixed-Signal IC Design
- CMOS
- EDA
- Mask Design
- OTA
- Differential Amplifiers
- Cadence
- PEX
- Schematic
- Physical Design
Jayasurya B. Summary
- Jayasurya B., based in Santa Clara, CA, US, is currently a Senior Mask Design Engineer at NVIDIA. Jayasurya B. brings experience from previous roles at MediaTek, Sensor Creations, Inc. and Southern Illinois University Edwardsville. Jayasurya B. holds a 2017 - 2019 Southern Illinois University Edwardsville. With a robust skill set that includes Physical Verification, ERC, ESD, Self Heating, Analog-to-Digital Converters (ADC) and more. Jayasurya B. has 2 emails and 1 mobile phone numbers on RocketReach.
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