Jayashree M Email
Analog Validation Engineer @ Texas Instruments India
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Jayashree M Location
- Tamil Nadu, India
Jayashree M Work
- Analog Validation Engineer @ (August 2025 - Present)
- CPC Core Head’24-25 @ (November 2024 - May 2025)
- Treasurer @ (September 2024 - May 2025)
- Workshops Head @ (October 2023 - September 2024)
- Analog Intern @ (May 2024 - July 2024)
- Head of External Affairs @ (July 2023 - July 2024)
- WIT scholar @ (November 2022 - December 2023)
- Workshops Coordinator @ (January 2023 - October 2023)
- Alumni Relations Coordinator @ (February 2023 - August 2023)
- Manager @ (January 2023 - July 2023)
- Research Intern @ (December 2022 - February 2023)
- Onfoot Mathematics Mentor @ (March 2022 - January 2023)
Jayashree M Education
- National Institute of Technology, Tiruchirappalli
Bachelor of Technology - BTech (Electronics and Communication Engineering)
2021-2025
Jayashree M Summary
- Jayashree M, based in Tamil Nadu, India, is currently a Analog Validation Engineer at Texas Instruments India. Jayashree M brings experience from previous roles at National Institute of Technology, Tiruchirappalli, Probe, NIT Trichy and Texas Instruments India. Jayashree M holds a 2021 - 2025 Bachelor of Technology - BTech in Electronics and Communication Engineering @ National Institute of Technology, Tiruchirappalli. Jayashree M has 1 emails on RocketReach.
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