Jayashree M Email
Analog Validation Engineer @ Texas Instruments India
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Jayashree M Location
- Tamil Nadu, India
Jayashree M Work
- 2025 -now Analog Validation Engineer @
- 2024 -2025 CPC Core Head’24-25 @
- 2024 -2025 Treasurer @
- 2023 -2024 Workshops Head @
- 2024 -2024 Analog Intern @
- 2023 -2024 Head of External Affairs @
- 2022 -2023 WIT scholar @
- 2023 -2023 Workshops Coordinator @
- 2023 -2023 Alumni Relations Coordinator @
- 2023 -2023 Manager @
- 2022 -2023 Research Intern @
- 2022 -2023 Onfoot Mathematics Mentor @
Jayashree M Education
- National Institute of Technology, Tiruchirappalli
Bachelor of Technology - BTech (Electronics and Communication Engineering)
2021-2025
Jayashree M Summary
- Jayashree M, based in Tamil Nadu, India, is currently a Analog Validation Engineer at Texas Instruments India. Jayashree M brings experience from previous roles at National Institute of Technology, Tiruchirappalli, Probe, NIT Trichy and Texas Instruments India. Jayashree M holds a 2021 - 2025 Bachelor of Technology - BTech in Electronics and Communication Engineering @ National Institute of Technology, Tiruchirappalli. Jayashree M has 1 emails on RocketReach.
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