Jayakrishnan Nair Location
- Sunnyvale, CA, US
Jayakrishnan Nair Work
- 2013 - now FPGA Validation Engineer @
- 2013 - now FPGA Engineer @
- 2013 - 2013 ASIC Verification Engineer trainee @ VeriFast Technologies
- 2010 - 2012 Graduate Assistant-Network Administrator @ Russ College of Engineering
- 2010 - 2012 Research associate @ Embodied Intelligence Group
Jayakrishnan Nair Education
- Ohio University 2009 - 2012
- Kerala University 2004 - 2008
Jayakrishnan Nair Skills
- Matlab
- Verilog
- system verilog
- Perl
- Shell Scripting
- VHDL
- C++
- UVM
Jayakrishnan Nair Summary
- Jayakrishnan Nair, based in Sunnyvale, CA, US, is currently a FPGA Validation Engineer at VSS Monitoring. Jayakrishnan Nair brings experience from previous roles at NETSCOUT, VeriFast Technologies, Russ College of Engineering and Embodied Intelligence Group. Jayakrishnan Nair holds a 2009 - 2012 Ohio University. With a robust skill set that includes Matlab, Verilog, system verilog, Perl, Shell Scripting and more. Jayakrishnan Nair has 2 emails and 1 mobile phone numbers on RocketReach.
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