Jay Raval Email
SoC Design Engineer @ Intel Corporation
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Jay Raval Location
- Hillsboro, OR, US
Jay Raval Work
- SoC Design Engineer @ (May 2022 - Present)
- SoC Design Engineer (DDG) @ (April 2021 - Present)
- SoC Design Engineer (IOTG) @ (August 2018 - Present)
- Engineer (QDSP Hexagon) @ (September 2016 - August 2018)
- Physical Design Engineer (Contractor) @ (May 2016 - September 2016)
- Project Trainee at DRDO (Anurag) @ (August 2015 - April 2016)
Jay Raval Education
- Gujarat Technological university
Bachelor’s Degree (BE(Electronics and Communication engineering))
- Vellore Institute of Technology
Master’s Degree (MTech (VLSI Design))
Jay Raval Skills
- ASIC
- CMOS
- Cadence Encounter
- Cadence RTL compiler
- Cadence Virtuoso
- Cadence nclaunch
- FPGA
- LabVIEW
- Logic Design
- Logic Synthesis
- Low-power Design
- Model-sim
- Perl
- Physical Design
- RTL Design
- Scripting
- Static Timing Analysis
- TCL
- Verilog
- Verilog-HDL
- Xilinx ISE
- Low Power Design
- Model Sim
- Verilog Hdl
Jay Raval Summary
- Jay Raval, based in Hillsboro, OR, US, is currently a SoC Design Engineer at Intel Corporation. Jay Raval brings experience from previous roles at Intel Corporation, Qualcomm and AMD. Jay Raval holds a Bachelor’s Degree in BE(Electronics and Communication engineering) @ Gujarat Technological university. With a robust skill set that includes ASIC, CMOS, Cadence Encounter, Cadence RTL compiler, Cadence Virtuoso and more. Jay Raval has 1 emails on RocketReach.
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