Jay Raval Email
SoC Design Engineer @ Intel Corporation
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Jay Raval Location
- Hillsboro, OR, US
Jay Raval Work
- 2022 -now SoC Design Engineer @
- 2021 -now SoC Design Engineer (DDG) @
- 2018 -now SoC Design Engineer (IOTG) @
- 2016 -2018 Engineer (QDSP Hexagon) @
- 2016 -2016 Physical Design Engineer (Contractor) @
- 2015 -2016 Project Trainee at DRDO (Anurag) @
Jay Raval Education
- Gujarat Technological university
Bachelor’s Degree (BE(Electronics and Communication engineering))
- Vellore Institute of Technology
Master’s Degree (MTech (VLSI Design))
Jay Raval Skills
- Verilog-HDL
- Cadence Virtuoso
- Model-sim
- Cadence Encounter
- Cadence nclaunch
- Cadence RTL compiler
- LabVIEW
- ASIC
- Static Timing Analysis
- FPGA
- RTL Design
- Logic Design
- Scripting
- TCL
- Low-power Design
- Xilinx ISE
- Physical Design
- CMOS
- Perl
- Verilog
- Low Power Design
- Model Sim
- Verilog Hdl
Jay Raval Summary
- Jay Raval, based in Hillsboro, OR, US, is currently a SoC Design Engineer at Intel Corporation. Jay Raval brings experience from previous roles at Intel Corporation, Qualcomm and AMD. Jay Raval holds a Bachelor’s Degree in BE(Electronics and Communication engineering) @ Gujarat Technological university. With a robust skill set that includes Verilog-HDL, Cadence Virtuoso, Model-sim, Cadence Encounter, Cadence nclaunch and more. Jay Raval has 1 emails on RocketReach.
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