Jay Lawlor Email & Phone Number
CPU Microcode and feature architect @ Intel Capital
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Jay Lawlor Location
- Hillsboro, OR, US
Jay Lawlor Work
- 2021 -now CPU Microcode and feature architect @
- 2020 -2021 Director, Customer Debug for Functional Validation, Xeon Server/DC @
- 2017 -2020 Design Engineering Manager @
- 1986 -1987 Member of technical staff @
Jay Lawlor Education
- Brigham Young University
Master Of Science (Electrical Engineering)
1982-1990
Jay Lawlor Skills
- Embedded Software
- Hardware Architecture
- Logic Design
- Computer Architecture
- C
- Debugging
- Perl
- Functional Verification
- RTL design
- Silicon Debug
- Microprocessors
- Processors
- Intel
- ASIC
- VLSI
- Verilog
- Integrated Circuit Design
- Circuit Design
- Mixed Signal
- Embedded Systems
- CMOS
- FPGA
- SoC
- VHDL
- EDA
- C++
- SystemVerilog
- Semiconductors
- Simulations
- Static Timing Analysis
- Microarchitecture
- IC
- Power Management
- Formal Verification For Post Silicon Debug
Jay Lawlor Summary
- Jay Lawlor, based in Hillsboro, OR, US, is currently a CPU Microcode and feature architect at Intel Corporation. Jay Lawlor brings experience from previous roles at Intel Corporation and CAECO. Jay Lawlor holds a 1982 - 1990 Master Of Science in Electrical Engineering @ Brigham Young University. With a robust skill set that includes Embedded Software, Hardware Architecture, Logic Design, Computer Architecture, C and more. Jay Lawlor has 1 emails and 1 mobile phone numbers on RocketReach.
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Jay Lawlor
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