Javad Ghasemi's Location
San Jose, CA, US
Javad Ghasemi's Work
- Design Verification Engineer @ Cadence Design Systems
- ASIC Design and Verification @ The University of New Mexico
- Image Sensor Characterization @ The University of New Mexico
- Teacher Assistant @ The University of New Mexico
- Firmware and FPGA design engineer @ Telecommunication Research Center (ITRC)
- Telecommunication Research Center (ITRC) @ Hardware design engineer
Javad Ghasemi's Education
- University of New Mexico School of Engineering
Doctor of Philosophy (PhD)
- University of Tehran
Master of Science (MSc) (Electrical, Electronics and Communications Engineering)
Javad Ghasemi's Skills
- SystemVerilog
- Computer Architecture
- Formal Verification
- Semiconductors
- ASIC
- Digital Electronics
- AMBA AHB
- Functional Verification
- UVM
- Assertion Based Verification
Javad Ghasemi's Summary
Javad Ghasemi, based in San Jose, CA, US, is currently a Design Verification Engineer at Cadence Design Systems, bringing experience from previous roles at University of New Mexico and Telecommunication Research Center (ITRC). Javad Ghasemi holds a Doctor of Philosophy (PhD) @ University of New Mexico School of Engineering. With a robust skill set that includes SystemVerilog, Computer Architecture, Formal Verification, Semiconductors, ASIC and more, Javad Ghasemi contributes valuable insights to the industry. Javad Ghasemi has 3 emails on RocketReach.
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