Jack Lam Email & Phone Number

Senior Principal Design Engineer @ Cadence Design Systems

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Jack Lam's Location

San Jose, CA, US

Jack Lam's Work

Senior Principal Design Engineer @ Cadence Design Systems
Senior Member of Technical Staff @ nusemi inc
Principal Ic Design Engineer @ Genapsys

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Principal Engineer @ Tektronix
Asic Hardware Design Engineer @ Tektronix
Contractor @ Ensphere Solutions
Principal Design Engineer @ Plato Networks
Senior Staff Analog Design Engineer @ Plato Networks
Design Engineer @ Plato Networks
Design Engineer @ Maxim Integrated

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Jack Lam's Education

Stanford University
Master of Science in Electrical Engineering (Electrical Engineering)
1998 - 1999
UC San Diego
Bachelor of Science in Electrical Engineering (Electrical Engineering)
1994 - 1998

Jack Lam's Skills

Mixed Signal
Analog Circuit Design
Analog

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ASIC
IC
Semiconductors
Circuit Design
CMOS
FPGA
Cadence Virtuoso

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Jack Lam's Summary

Jack Lam, based in San Jose, CA, US, is currently a Senior Principal Design Engineer at Cadence Design Systems, bringing experience from previous roles at Nusemi Inc, Genapsys, Inc. and Tektronix. Jack Lam holds a 1998 - 1999 Master of Science in Electrical Engineering in Electrical Engineering @ Stanford University. With a robust skill set that includes Mixed Signal, Analog Circuit Design, Analog, ASIC, IC and more, Jack Lam contributes valuable insights to the industry. Jack Lam has 2 emails on RocketReach.

Jack Lam Email Address

Found 2 email address listings:

Jack Lam Phone Number

Found 1 phone number:

408420XXXX

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