Jack Lai Location
- California, United States
Jack Lai Work
- 2024 - now AMS layout @
- 2021 - 2023 Sr. Mixed Signal Layout Lead @
- 2019 - 2021 Sr. Analog Layout Design Lead @
- 2016 - 2019 PLL Mask Design Lead @
- 2013 - 2016 Senior Mask Designer @
- 2010 - 2013 IC Mask Designer @ Touchstone Semiconductor
- 2010 - 2011 Technical of Things @
Jack Lai Education
- California State Polytechnic University
Bachelor Of Science (Real Estate, Law, Finance)
2005 - 2010 - Silicon Drafting Institute
(Design)
Jack Lai Skills
- IC
- Mixed Signal
- LVS
- DRC
- ASIC
- Floorplanning
- Analog
- FinFET
- Analog Circuit Design
- Physical Design
- Integrated Circuit Design
- Integrated Circuits (IC)
- CMOS
- Cadence Virtuoso
- Cadence
- BiCMOS
- Power Management
- Physical Verification
- Microprocessors
- PLL
- Dracula
- Cadence Virtuoso XL
- Comparators
- Application-Specific Integrated Circuits (ASIC)
- Layout Versus Schematic (LVS)
- Design Rule Checking (DRC)
- Microsoft Office
- Layout Versus Schematic Lvs
- Design Rule Checking Drc
- Integrated Circuit
- Integrated Circuits Ic
- Application Specific Integrated Circuits Asic
- Integrated Circuits
- Layout Versus Schematic
- Design Rule Checking
- Application Specific Integrated Circuits
Jack Lai Summary
- Jack Lai, based in California, United States, is currently a AMS layout at Marvell Technology. Jack Lai brings experience from previous roles at PsiQuantum, Apple, Intel Corporation and SanDisk, a Western Digital Brand. Jack Lai holds a 2005 - 2010 Bachelor Of Science in Real Estate, Law, Finance @ California State Polytechnic University. With a robust skill set that includes IC, Mixed Signal, LVS, DRC, ASIC and more. Jack Lai has 2 emails and 2 mobile phone numbers on RocketReach.
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