Jack Chiang Email
Staff Packaging Engineer @ Marvell India
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Jack Chiang Location
- San Jose, CA, US
Jack Chiang Work
- 2024 -now Staff Packaging Engineer @
- 2021 -2024 Semiconductor Research Scholar, Packaging @
- 2022 -2023 Photonic Packaging Co-op Engineer @
- 2020 -2021 Research Assistant @
- 2018 -2019 Packaging Engineer @
- 2014 -2016 Research Assistant @
- 2014 -2014 Intern @ Wele Mechatronic Co., Ltd.
Jack Chiang Education
- Purdue University
Doctor's Degree (Mechanical Engineering)
2020-2024 - Kwansei Gakuin University
(Japanese Studies)
2016-2017 - National Taiwan University
Master's Degree (Mechanical Engineering (Manufacturing division))
2014-2016 - National Tsing Hua University
Bachelor's degree (Mechanical Engineering)
2009-2014
Jack Chiang Skills
- Failure Mode and Effects Analysis (FMEA)
- Reliability
- Cost Savings
- Flip Chip
- Numerical Analysis
- Electronics Packaging
- MOOSEframework
- Materials Science
- Mechanical Engineering
- AutoCAD
- Autodesk Inventor
- Matlab
- ANSYS
- Microsoft Office
- English
- Research
- Japanese
- CATIA
- Manufacturing Engineering
- Semiconductor Process
- Python (Programming Language)
- python
- C++
Jack Chiang Summary
- Jack Chiang, based in San Jose, CA, US, is currently a Staff Packaging Engineer at Marvell Technology. Jack Chiang brings experience from previous roles at SRC Research Scholars Program, Nokia, Purdue University and Texas Instruments. Jack Chiang holds a 2020 - 2024 Doctor's Degree in Mechanical Engineering @ Purdue University. With a robust skill set that includes Failure Mode and Effects Analysis (FMEA), Reliability, Cost Savings, Flip Chip, Numerical Analysis and more. Jack Chiang has 2 emails on RocketReach.
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