Harshil Patel's Location
California, United States
Harshil Patel's Work
- Digital Verification Engineer @ Allegro MicroSystems
- Graduate Research Assistant @ San Jose State University
- FPGA Design Engineer Intern @ Colfax International
- FPGA Design Engineer Intern @ Colfax International
- Production Engineer @ Electronic Systems Of Illinois
- Internship Trainee @ Schneider Electric
Harshil Patel's Education
- San Jose State University
Master's degree (VLSI (Electrical and Electronics Engineering))
2018 - 2020 - Gujarat Technological University
Bachelor's degree (Electrical Engineering)
2013 - 2017
Harshil Patel's Skills
- Verilog
- Perl
- Linux
- ANSYS
- Matlab
- Python
Harshil Patel's Summary
Harshil Patel, based in California, United States, is currently a Digital Verification Engineer at Allegro MicroSystems, bringing experience from previous roles at San Jose State University, Colfax International and Electronic Systems. Harshil Patel holds a 2018 - 2020 Master's degree in VLSI (Electrical and Electronics Engineering) @ San Jose State University. With a robust skill set that includes Verilog, Perl, Linux, ANSYS, Matlab and more, Harshil Patel contributes valuable insights to the industry. Harshil Patel has 3 emails on RocketReach.
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