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Harm Peters Location
Eindhoven, NB, NL
Harm Peters Work
2026 -now Senior Vice President Silicon @
2025 -2026 VP Silicon Design Engineering @
2018 -2025 Tech Lead Hardware Design and Implementation (NEX Xeon and Networking Engineering Group) @
2011 -2018 Physical Design manager Imaging IP (IPG Imaging and Camera Technology Group.) @
2007 -2011 Team leader and senior VLSI engineer @
1992 -2007 Senior IC design engineer @ Philips Research
Harm Peters Education
Fontys University of Applied Sciences
Bachelor of Engineering - BE (Electrical Engineering)
1988-1992
Harm Peters Summary
Harm Peters, based in Eindhoven, NB, NL, is currently a Senior Vice President Silicon at Euclyd. Harm Peters brings experience from previous roles at Euclyd, Intel Corporation and Silicon Hive. Harm Peters holds a 1988 - 1992 Bachelor of Engineering - BE in Electrical Engineering @ Fontys University of Applied Sciences. Harm Peters has 2 emails and 1 mobile phone numbers on RocketReach.
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